1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having an error correction function.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) mounted on computer equipments, a necessary memory capacity rapidly increases in recent years. In response to the increase in memory capacity, a miniaturization technique progresses. However, when the miniaturization technique progresses, reliability in a memory cell is reduced. In order to prevent the reduction in reliability, the following redundant technique has been used. An extra memory region (redundant region) is provided in a memory cell array. In place of a defective memory cell in a normal memory cell array region, a non-defective memory cell in the redundant region is selected to relieve defects. According to this technique, although the reduction in the reliability of products themselves can be prevented, the following problem occurs in recent years. In the memory cell requiring a refresh operation, such as a DRAM cell, a data retention time is suddenly degraded, and thereby defects occur after packaging or shipping of products.
One example of countermeasures for the defects caused by data retention time degradation includes a method of mounting an ECC (Error Checking and Correcting) function. In the method of mounting a commonly used ECC function capable of 1-bit error correction, even when read-out data have an error of 1-bit, the error can be corrected using the ECC function. Further, a method of mounting the ECC function to allow it to take over the repair of defects by the redundant technique is also considered. More specifically, when the error within the ECC code (e.g., hamming code) is a 1-bit error, the error correction is performed by each read-out operation in a state of a 1-bit error without using the redundant region.
Therefore, a single-bit defect (it means a defect that not two or more defects but only one defect is generated by one read-out operation due to BL (bit line) short/open) to some extent can be repaired without using the redundant region. As a result, even defective chips which are heretofore discarded due to excessive amounts of defective bits that cannot be repaired using a predetermined redundant region can be changed into non-defective chips. Therefore, this can contribute to improvement in the yield.
However, when the number of single-bit defects of which the repair by the redundant technique can be taken over by the ECC function is too large, a probability of repair defective bits caused by a data retention time degradation is reduced. Accordingly, what becomes important here is as follows. The first point is that the number of defective bits of which the repair by the redundant technique can be taken over by the ECC function is determined at the time of packaging or shipping chips as products. The second point is that the test operation can be performed.
For that purpose, a semiconductor memory device having a counter, a register, a comparison circuit, and an output circuit is required. Each element has the following function. The counter can count the number of error corrections. The register can set the upper limit of the number of error corrections. The comparison circuit can compare values of the counter with those of the register. The output circuit can output the comparison results.
The semiconductor memory device having the above-described functions is disclosed, for example, in Japanese Unexamined Patent Publication No. 49-60450 (p. 3, FIG. 2), Japanese Unexamined Patent Publication No. 1-94599 (pp. 4-5, FIG. 1), and Japanese Unexamined Patent Publication No. 6-131884 (paragraph numbers [0006] to [0008], and FIG. 1). The semiconductor memory device has the following configuration.
FIG. 9 shows a configuration of a conventional semiconductor memory device.
A conventional semiconductor memory device 20 has a data bit section 21, a parity bit section 22, an error correction circuit 23, a parity calculation circuit 24, a counter 25, a register 26, a comparison circuit 27, an output circuit 28 and an input circuit 29. The data bit section 21 stores a data bit out of data stored in a memory cell array comprised of memory cores (not shown). The parity bit section 22 stores a parity bit out of data stored in a memory cell array comprised of memory cores (not shown). The error correction circuit 23 performs an error correction with reference to the data bit and the parity bit. The parity calculation circuit 24 generates a parity bit according to input data, for example, by the operation based on a hamming code. The counter 25 counts the number of error corrections. The register 26 stores an upper limit of the number of error corrections. The comparison circuit 27 compares the counted number of error corrections with the upper limit of the number of error corrections stored in the register 26.
In the conventional semiconductor memory device 20, the error correction circuit 23 performs a 1-bit error detection and a 1-bit error correction with reference to, for example, 64 data bits and 7 parity bits. When detecting a defective bit, the circuit 23 inverts the bit for the error correction and then, outputs the results through the output circuit 28. The counter 25 counts the number of error corrections when a count start signal is inputted during the test operation. The comparison circuit 27 compares the number of error corrections with the upper limit of the number of error corrections previously stored in the register 26, and thereby judging whether or not the number of error corrections exceeds a predetermined upper limit. When the number of error corrections exceeds the upper limit, the output circuit 28 generates an alarm.
The conventional semiconductor memory device, however, has some problems as described hereinbelow. The first problem is as follows. Even if the number of error corrections counted during the test operation is too large or too small with respect to the set upper limit, the upper limit cannot be arbitrarily set. This upper limit is an upper limit of the number of the defective bits of which the repair by the redundant technique can be taken over by the ECC function. Accordingly, defective bits beyond the upper limit are repaired by the redundant region. Therefore, the second problem is as follows. When the upper limit is too small, many redundant regions are required depending on the number of error corrections. On the contrary, when the upper limit is too large, a probability of relieving the defective bits caused by a data retention time degradation is reduced in the case where the number of error corrections is large.
The third problem is as follows. Due to deterioration with time of the memory cell, the number of the defective bits after the packaging or shipping increases more than that during the test operation in some cases. Despite this, there is no section for grasping this situation.
The fourth problem is as follows. Depending on the test pattern, the same address data are accessed two or more times in some cases and at this time, the defective bit is carelessly counted two or more times.